Prateek Kumar - CAD & Methodology Engineer

Specialist CAD & Methodology Engineer with over 5 years of demonstrated excellence at industry leaders Intel and Synopsys, architecting and deploying robust design automation frameworks that serve as critical force multipliers for global SoC design teams. Proven expertise in end-to-end IP hardening, signoff flow development, and methodology innovation using systematic approaches to constraint management, quality validation, and regression automation. Recognized with 11 major awards for driving tangible improvements in productivity, quality, and tool stability. Combines deep technical mastery of EDA tools with practical software engineering best practices in Python and Tcl to solve complex design convergence challenges.

Synopsys India Pvt. Ltd. – R&D Engineering, Staff Engineer

July 2024 – Present

As the sole Backend Owner for the CDM IP, architected and executed the complete physical design flow from RTL synthesis (Design Compiler/Fusion Compiler) through place-and-route to final GDSII signoff (PrimeTime STA), implementing a hierarchical constraint management strategy and clock domain crossing (CDC) verification protocols to ensure first-pass integration success for 2 major SIP releases.
Led IP integration verification by developing a suite of targeted testcases and automated regression environments to validate hardened IPs within complex SoC contexts, ensuring compatibility and functional correctness post-integration.
Engineered a comprehensive suite of 15+ modular automation scripts in Python and Tcl for design rule checking, pre-placement feasibility analysis, and post-placement congestion assessment, adhering to software development best practices (version control with Git, modular code, comprehensive logging) which slashed average manual review time by 4 hours per IP run and enhanced flow scalability and runtime efficiency.
Authored and maintained the definitive Backend User Guide and comprehensive flow documentation, establishing a centralized knowledge repository that standardized best practices and reduced onboarding time for new team members by an estimated 30%.
Enabled and optimized Fishtail (TCM) and VCLP power analysis flows across a portfolio of 8+ IPs (including HIPs and SIPs), developing automated regression suites and data visualization scripts in Python to generate detailed area, utilization, and timing reports that directly informed critical PPA trade-off decisions for 3 successful tapeouts.
Synthesized and generated release-ready netlists for the latest IP versions using Design Compiler and Fusion Compiler, enforcing stringent quality checks and formatting standards to ensure downstream compatibility.
Generated detailed Resource Utilization and Area reports for HIPs and SIPs, providing critical data to architects and design managers for early-stage planning and resource allocation.
Acted as the primary technical contact for backend issue resolution, driving the diagnosis and closure of 50+ high-priority BE JIRA tickets through systematic root-cause analysis and collaborating effectively with cross-functional teams to maintain project velocity.

Intel – SoC Design Engineer (CAD/Methodology)

July 2021 – July 2024

Deployed and supported the Flow and Methodology for various Frontend and SD Handoff flows across multiple IP Teams, ensuring standardization and reliability in the early design stages.
Served as the primary technical contact for Synthesis and LEC flows within the Front-end scope, providing expert-level enablement, debugging support, and troubleshooting to ensure successful flow execution for design teams.
Primary owner for the deployment of Netlist quality check flows run on top of pt_shell, developing and maintaining checkers that ensured netlist integrity before handoff to physical design teams.
Led the migration of 5 core methodology flows (H2B, LEC, IPQC) from legacy Perl to modern object-oriented Python, implementing configuration-driven execution, comprehensive error handling, and unit testing frameworks that resulted in an annual reduction of over 200 engineer-hours in maintenance overhead while substantially improving runtime reliability.
Supported and contributed to the development of the VISA flow, enhancing its capabilities and stability for broader team adoption.
Worked closely with the execution team to provide rapid, customized automation solutions in Python/TCL for emergent project needs, improving task efficiency and reducing manual effort.
Collaborated with global methodology teams in an Agile framework to discuss, propose, and review 4 new methodology solutions that improved overall design quality and enhanced flow ease of use for a wide user base.
Developed numerous automation solutions using Python and TCL to streamline repetitive tasks, improve data consistency, and accelerate the design feedback loop for engineers.

Intel – CAD Engineer

July 2020 – July 2021

Developed SD handoff flows responsible for the automated generation of RTL Lists and Hard-IP lists, crucial data sets consumed by downstream Synthesis flows to ensure correct and complete design processing.
Designed and deployed the syn2sim signoff filelist generation flow for Conformal LEC verification, a critical quality gate that implemented automated consistency checking between simulation and synthesis views and was adopted as a standard for 2 major project turn-ins, effectively preventing late-finding functional mismatches.
Spearheaded the Development & Deployment of Netlist Quality check flows in the Front-end scope, creating a robust framework for early defect detection.
Developed complex task file generation scripts to efficiently run multi-partition tasks on a Flow-manager, optimizing compute resource utilization and job scheduling for large-scale designs.
Provided comprehensive Flow support for a range of tools: for Synthesis (Fusion Compiler and Design Compiler) including full/lite setup and backend collateral; for PrimeTime netlist quality checks; and for LEC (Conformal) including fevlite, RTL2RTL comparison, and syn2sim signoff flow development.
Organized and led regular Workgroups with Design teams to gather issues, provide quick solutions, and collect enhancement requests, fostering a collaborative troubleshooting environment.
Built and deployed automated Netlist Quality Check flows using PrimeTime shell (pt_shell), creating a plug-and-play checker architecture with standardized reporting that expanded the validation suite for frontend teams and ensured consistent quality standards across 5+ major projects.

Intel – Technical Graduate Intern

June 2019 – June 2020

Provided support and contributed to the development of the FEBE (Frontend to Backend handoff) Flow, gaining foundational understanding of the critical data handoff process between design stages.
Worked on the development of an automated RTL list generation utility based on the VCS compilation tool, helping to streamline a previously manual step in the flow setup.
Developed a flow to automatically generate the v2k config file required for synthesis directly from VCS elaboration information, reducing potential configuration errors and saving setup time for designers.

HIP Flow Bring-up Award

Synopsys (2024). Recognized for Execution Excellence in enabling new methodology.

SIP Flow Bring-up Award

Synopsys (2024). Recognized for Smarter Teamwork skills.

Intel DRA: Ticket Backlog Reduction

Awarded for leading an initiative that achieved a 50% reduction in customer ticket backlogs.

Intel DRA: New Handoff Methodology

Awarded for enabling a new methodology providing a cohesive environment and seamless workflow.

Intel DRA: Standardized FE Data Capture

Awarded for delivery of standardized data capture and indicators for major projects and customers.

Intel DRA: Syn2Sim Sanity Checks

Awarded for initiating the addition of syn2sim checks to the HW turn-in process, preventing late-finding bugs.

Intel Customer Excellence Award

Recognized for outstanding support in Q1, Q2, and Q3 of 2023.

Intel DRA: Tool Stability

Awarded for improving tool stability and developing expert users, reducing tickets by 5X.

Intel ML Hackathon – 2nd Place

Company-wide competition (Aug 2021). Applied ML techniques to a design challenge.

Multiple Intel Tap-In Awards

Received numerous spot awards for critical contributions, automation scripts, and collaboration.

EDA Tools & Platforms

Synopsys PrimeTime (STA) Fusion Compiler Design Compiler Conformal LEC / Formality VCS Fishtail / TCM Flows VCLP

Programming, Scripting & DevOps

Python (OOP, Pandas) Tcl Perl Shell Scripting (Bash) Git JIRA Linux/Unix Environment

Design Methodologies & Flows

Static Timing Analysis (STA) Logic Synthesis & Optimization Formal Verification (LEC) Physical Design Flows Power Integrity Analysis (VCLP) Netlist & RTL Quality Checks Frontend/Backend Handoff IP Hardening & Release

Core Competencies & Best Practices

CAD Flow Architecture Methodology Development Automation Framework Design Constraint Management Quality Assurance & Signoff Technical Documentation Cross-functional Collaboration Root-Cause Analysis

Master of Technology (M.Tech) in VLSI

Malviya National Institute of Technology (MNIT), Jaipur | 2018 - 2020

Advanced coursework in Digital VLSI Design, CMOS Analog Design, Low-Power VLSI, and VLSI Testing, providing a strong theoretical foundation for practical CAD and methodology challenges.

Bachelor of Technology (B.Tech) in Electronics & Communication Engineering

National Institute of Technology (NIT), Kurukshetra | 2012 - 2016

Core engineering curriculum with fundamentals in Digital Electronics, Microprocessors, Signal Processing, and Communication Systems.